AN620 application note on-board programming of otp eprom by franco morandi may 1996 1/8 in recent years interest has been growing in on-board programming of otp eprom memories. there are two main factors which have stimulated this interest: the growth of the flash memory market and the increased use of surface mount packages. the growth of the flash memory market uv eproms and otp eproms offer a higher degree of flexibility compared to mask roms. this is due to their ability to be electrically programed and, in the case of the uv eprom, erased by exposure to uv light, then re-programed. the ability to electrically program these parts is the most important feature which allows uv eproms or otp eproms to be seen by users as roms which are programmable at the f inal moment in the exact quantity required. programming of the memories is mainly done by the use of dedicated programing equipment using software algorithms which match those specified by the major chip makers. fast programming services are also offered by testing houses and by vendors themselves for a small price premium. the plastic packaged otp eproms are therefore regarded by many as flexible roms. programming of otp eproms in the application board itself, rather than in the dedicated programming equipment, has not been common until the recent introduction of flash memories. one of the important features of the flash memory is its programability (and erase and re-programability) on board, in the application. with the growth in the use of flash memories today, otp eproms are seen not only as flexible roms but now also as low cost flash memory alternatives. for this reason many customers plan to use otp eproms to replace flash memories in low end applications as soon as production levels increase and codes become stable. these otp eproms are mounted on board and thus must be programmed, like the flash memory, in the application. the increased use of surface mount packages while the traditional dual-in-line insertion packages, both ceramic and plastic, remain popular, there is a strong trend towards surface mounting plcc and tsop types which offer small footprints and easy automatic assembly. the loading of these packages in the dedicated programming equipment and subsequent transfer to the application board, however, presents significant problems and expensive, dedicated handlers are needed. users therefore prefer to abandon off line programming and chose on-board programming techniques. programming a uv eprom or otp eprom cell is performed by injecting electrons onto the cell mos transistor floating gate. a voltage in excess of 6v must be applied to the drain of the cell, together with above 12v on the control gate to get an average energy of the electrons sufficiently large to make them jump the oxide barrier at a significant rate for a fast programming speed. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
obp and product testing when uv eprom or otp eprom products are programmed in dedicated programming equipment the v cc supply voltage is raised to 6v to 6.5v. this level of v cc cannot generally be applied to a board containing the otp eprom due to the possible damage to other components. recent designs of uv eprom and otp eproms however derive the internal 6v or more used during the write mode from the v pp supply and so are independent of the v cc voltage applied. in fact cell writing can normally take place even if the v cc is 5v or lower. this feature is not, however, sufficient to guarantee on-board programming (obp) performance. there remains the need to verify the memory content of programmed cells. when the read verify is performed with a 5v v cc supply clearly this ensures that the cells are programmed to logic 0 at least up to 5v, but not more. a high level of confidence remains that the cells, programmed with the internal 6 volts derived from the 12.75v v pp supply, are in fact over-programmed with a satisfactory margin and would display the correct pattern if verified at above 5v v cc , but to guarantee this to a high quality level is not poss ible with a read verify at 5v. just one cell in 4 billion which is harder to program and is marginally written is sufficient to give reject quality of 1000 ppm for 4 megabit otp eproms! so the challenge to provide obp features for otp eproms is not one of programming, but of testing and verification of the programmed pattern. the question that must be answered is "is it possible to guarantee the quality of the memory content when they are programmed at 5v v cc on board?". reliable otp eproms the use of obp for programming uv eproms or otp eproms is to related to the confidence in the supplier to deliver a reliable and consistent product. the following section outlines the main issues which have been developed and are used by sgs-thomson to build confidence in the products ability to perform r eliably af ter on-board programming has been used. wafer level testing while built-in reliability is obtained for our uv eprom and otp eprom products through robust design, proven and stable processes and extensive characterisation, there are some spec ific routines that are used to ensure the quality of the product for on-board programming. gate stress and drain stress the integrity of the critical thin oxides is checked by specially developed stress tests, these are performed by applying a fixed voltage to either the control gate (gate stress) or to the drains of the cells (drain stress). the gate stress is done firstly on the virgin cells (all "1"s) and then on programmed cells (all "0"s). figures 1, 2, 3 describe the different stresses, the measurements and the specific defects they aim to detect or screen out. these tests are particularly effective in screening out the chips which are potentially prone to programming errors because the same kind of stresses are applied to the cells during normal write operations. all the cells of the same row share a common word line and when a byte is programmed all those cells not b eing written, in the row which is at high v pp , are submitted to a gate stress and could evidence the spurious effect of charge gain for virgin cells or charge loss for written cells. a similar argument applies for the cells of a column, biased at the same v cc through the common bit line. the stress times have been chosen to be equivalent to the total duration of the critical conditions encountered whenever writing of a whole memory pattern occurs. 2/8 AN620 - application note www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
ai01342 v pp source e _ drain gnd gate stress, logic '1' - v pp = 13v - t = 0.6 sec ( < 2mbit) t = 1.0 sec ( > 4mbit) detects 'charge gain' through the gate oxide figure 1. gate stress testing at logic 1 ai01343 v pp source e _ drain gnd gate stress, logic '0' - v pp = 13v - t = 0.5 sec ( < 2mbit) t = 1.0 sec ( > 4mbit) detects 'charge loss' through interpoly oxide figure 2. gate stress testing at logic 0 ai01344 source e _ drain gnd drain stress, logic '0' - v pp = 6.5v - t = 0.5 sec (256 kbit) t = 1.0 sec (> 512 kbit) detects 'charge loss' through gate oxide in the drain region v cc figure 3. drain stress testing at logic 0 3/8 AN620 - application note www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
byte verify each byte used during the wafer level program- ming sequence is verified for both all "1"s before writing and for the correct pattern after writing. these two checks together ensure that the cells are programmable. moreover the second check is made at a v cc of 6.5v in margin mode ? , a condition corresponding to such a strong over pro- gramming that the cells reaching it (that is the good cells) are definitely not hard for writing. retention bake the flow of the sequence of wafer level testing is shown in figure 4. the first part ends with the memory matrix fully programmed (all "0"s). the wafers are then submitted to a 48 hour storage at 250 c for a overstress retention bake. during the second test sequence the all "0"s pattern is verified at a v cc of 6.5v and all chips failing the correct pattern, due to cells which have lost their charge, are rejected. this test at 250 c is equivalent to a test of more than 5 years at 70 c operating tem- perature. margin mode verify the uv eprom, otp eprom and flash mem- ory products of sgs-thomson have two different read modes, the normal read mode and a special margin mode which is automatically set during writing. this is a unique feature based on a patent of 1985 (1) and a paper given in 1988 (2) which disclosed the underlying principle of the design concept. the design uses an off-set current in the sense circuitry to shift the threshold detection for verification of programming of each cell. the relationship of the array cell current to the current in a reference cell is shown in figures 5 and 6. figure 5 shows the normal read mode while figure 6 shows the new margin mode relation- ship with the off-set current present which makes the verify of a programmed "0" in the cell at a new higher threshold level. in figure 5 a threshold shift of 1v is sufficient to make i write lower than i ref , while in figure 6 for the margin mode a shift of 2v is needed. this assures a margin of 1v in the programmed threshold, or "0" level, of the cell. ai01345 1st test - all '0's 48 hours bake 250 o c wafer level tests assembly 2nd test erase to all '1's figure 4. otp eprom testing flow chart ai01346 1 2345678 v gs (v) i write i ref i erase i ds ( m a) "1" "0" figure 5. cell current in read mode 4/8 AN620 - application note www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
the same concept of margin mode verify con- tinues to be used in all of the currently produced uv eproms and otp eproms, although it is not implemented in the same way. todays uv eproms, otp eprom and flash memory prod- ucts use a more sophisticated concept that allows precise setting of the reference cell current during testing. they have again a programming verify mode or margin mode which is different from the normal read mode to ensure a programming mar- gin. electrical characterisation of the 4 megabit eprom products shows that a minimum thres hold shift of a cell equal to 2.7v is ensured when they are tested at v cc = 5v in margin mode, the same result would be guaranteed at a v cc = 6v in read mode. conversely the 5v verify in read mode guarantees only a 2.2v shift in the cell threshold, or a programming shift of 0.5v lower. this is illustrated in figure 7. in conclusion, programming at v cc = 5v with mar- gin mode pattern verify automatically gives a programming margin needed to avoid in system noise problems and gives a guarantee of long term pattern stability. ai01347 1 2345678 v gs (v) i write i ref i erase i ds ( m a) "1" "0" figure 6. cell current in verify mode ai01348 1.07 1.26 1.41 1.63 1.98 2.34 2.67 3.11 2.94 3.31 3.68 0 1 2 3 4 5 7 8 6 0 1 2 3 4 5 7 8 6 v cc read mode v cc margin mode threshold shift v cc read mode v cc margin mode v cc = 5v figure 7. 4mbit eprom threshold shift 5/8 AN620 - application note www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
suggested programming algorithm for on-board programming, a modified condition of the presto ii programming algorithm is used. this algorithm provides a faster, but still reliable programming operation, and is further in line with the in-circuit programming time for the equivalent flash memory device. the standard presto ii algorithm is still available for use in device programmers. figure 8 shows the new algorithm for on-board programming and can be compared to the normal presto ii algorithm shown in figure 9. the new conditions for presto obp programming are that the ap plied v cc is now 5v, and the v pp = 12.75v is applied not only during byte-by-byte verify but also during the f inal pattern verify in order to maintain the read in margin mode and ensure the cells are all programmed to the margin mode threshold after the whole programming sequence and have not been affected by any gate or drain stresses that could cause a shift of the programmed charge levels. the duration of the programming pulse is reduced to 10 m s, with a maximum repetition cycle number of 25 in the case of non-validation of the data programmed. a final over-programming pulse of 10 m s is needed before the final v alidation pass of all memory cells in the margin mode, but at the 5v(3v) level. if possible, the v cc applied should be as high as is possible (up to 5.5v for 5v systems, 3.5v maximum for 3v systems) while remaining suitable for other parts in the circuit of the application. as shown previously, a higher v cc provides a higher level of validation of correct programming. ai00738b n = 0 last addr verify e = 100 m s pulse ++n = 25 ++ addr v cc = 6.25v, v pp = 12.75v fail check all bytes 1st: v cc = 6v 2nd: v cc = 4.2v yes no yes no yes no set margin mode reset margin mode figure 9. presto ii programming flowchart ai01349 n = 0 last addr verify ? e = 10 m s pulse ++n = 25 ++ addr v pp = 12.75v fail check all bytes v pp = v cc yes no yes no yes no set margin mode e = 10 m s pulse figure 8. on-board programming flowchart 6/8 AN620 - application note www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
important! compatibility issues compatibility issues may arise when using the otp eprom to replace a single supply flash memory device (for example, for 4 megabit devices, the m27c405 otp eprom and the m29f040 single supply flash memory). in this case the v pp pin of the m27c405 takes the position of the write enable ( w) control input of the m29f040. this pin of the flash memory can only accept normal ttl voltage levels and not the high 12.75v, so care must be taken in the implementation of the design if it is intended to eventually replace the flash memory with otp eprom once the contents are stable and production volumes and price pressure require the lower cost alternative otp eprom. in addition, the m27c512 (512k) and m27c801 (8 megabit) products have to be treated a little differently. in order to make them compatible with the 28 or 32 lead packages these two products share the same pin for v pp and output enable ( g). thus a high v pp level cannot be set for reading, which requires g to be low. for these products the margin mode must be set by a specific sequence of signals shown in figure 10 before starting programming and through the final pattern verify. references (1) "device for the verification of the memory cells on the basis of the threshold drop obt ainable during writing" , giulio casagrande, roberto gastaldi, patent filed with priority date 3/28/85 (2) roberto gastaldi et al, " a 1 mbit cmos eprom with enhanced verification" , ieee journal of solid state circuits, vol 23, no 5, october 1998 ai00736b ta9hvph tvpxa9x a8 e gv pp a10 set v cc tvphel ta10leh texvpx ta10heh a9 a10 reset texa10x figure 10. margin mode setting ac waveforms for products with v pp and g on the same pin. 7/8 AN620 - application note www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specification mentioned in this publication are subject to change without not ice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical comp onents in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1996 sgs-thomson microelectronics - printed in italy - all rights reserved sgs-thomson microelectronics group of companies australia - brazil - canada - china - france - germany - hong kong - i taly - ja pan - korea - malaysia - malta - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. 8/8 AN620 - application note www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
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